1. Field of the Invention
The present invention relates to a bus detection and control method and a bus detection and control device thereof, and more particularly, to a bus detection and control method and a bus detection and control device thereof capable of forcing a slave to maintain in an initial state after a signal transmission error occurred in a mobile industry processor interface (MIPI) bus and wait for receiving a signal outputted by a host until the host also returns to the initial state, to prevent signal transmission errors.
2. Description of the Prior Art
With the development of science and technology, handheld devices such as smart phones, personal digital assistants (PDA), etc. integrate more and more communication and displaying techniques, to realize various application functions. In order to simultaneously control various application functions, it requires a high-speed processing interface between a processor and a display panel (i.e. between a host and a slave) of a smart handheld device, to speed up data transmission and thus improve display quality or touching functions of the panel. The mobile industry processor interface (MIPI) is a high-speed serial interface used widely in current industry. However, in the mobile industry processor interface system, the host and the slave may consider the status of a single mobile industry processor interface bus shared for data transmission between the host and the slave differently, which cause transmission errors.
For example, please refer to FIG. 1, which is a schematic diagram of a conventional mobile industry processor interface system 10. As shown in FIG. 1, in the mobile industry processor interface system 10, a host 100 is coupled to a slave 104 with a mobile industry processor interface bus 102 for data transmission.
For this structure, please refer to FIG. 2A to 2C. FIG. 2A is a signal diagram of a mobile industry processor interface bus 102 when the host 100 transmits high-speed differential signals. FIG. 2B is a signal diagram of the mobile industry processor interface bus 102 when the host 100 performs bus turnaround (BTA). FIG. 2C is a schematic diagram of operations of the mobile industry processor interface system 10 when the host 100 performs bus turnaround. As shown in FIG. 2A, the mobile industry processor interface bus 102 includes transmission lines DN0, DP0. First, when the host 100 and the slave 104 are in initial states and do not transmit data, the initial state of the mobile industry processor interface bus 102 is an LP11 stop state (i.e. both the transmission lines DN0, DP0 are with logic high in a low power transmission mode). Then, the host 100 transmits a high-speed transmission sequence as shown in the dotted frame of FIG. 2A which indicates the slave 104 that the host 100 is about to start transmitting high-speed differential signals to write instructions or data. Therefore, the slave 104 may be set to a high-speed transmission mode to receive high-speed differential signals transmitted by the host 100 and operate accordingly. When transmission of the high-speed differential signals is completed or a predefined high-speed transmission timer is time out, the mobile industry processor interface bus 102 returns to the LP11 stop state again (the host 100 and the slave 104 are also set to the initial state and do not transmit data).
On the other hand, as shown in FIGS. 2B and 2C, since the host 100 and the slave 104 share the mobile industry processor interface bus 102 for data transmission, the host 100 transmits a bus turnaround sequence shown in the dotted frame of FIG. 2B indicating the slave 104 that the host 100 starts reading back data when the host 100 intends to read back data or statuses of the slave 104. At this moment, the control authority over the mobile industry processor interface bus 102 is transferred to the slave 104, which means the host 100 and the slave 104 are set from a transmitting end and a receiving end to a receiving end and a transmitting end, respectively (as shown in FIG. 2C). Accordingly, the slave 104 transmits data or status signals required by the host 100 to the host 100 (shown as the dotted lines of the transmission lines DN0, DP0 in FIG. 2B).
However, please refer to FIGS. 3A and 3B. FIG. 3A is a signal diagram of contention occurred in the mobile industry processor interface bus 102 when the host 100 performs bus turnaround. FIG. 3B is a schematic diagram of operations of the mobile industry processor interface system 10 when contention is occurred in the mobile industry processor interface bus 102. As shown in FIGS. 3A and 3B, when bus turnaround is completed such that the slave 104 has control authority over the mobile industry processor interface bus 102 and starts transmitting data to the host 100, if the host 100 incorrectly considers owning the control authority over the mobile industry processor interface bus 102 (the host 100 switches from the receiving end to the transmitting end by itself) and starts transmission (e.g. high-speed differential signal transmission as the latter parts of the solid lines of the transmission lines DN0, DP0 in FIG. 3B), signals transmitted from the host 100 to the slave 104 undergo contention against signals transmitted from the slave 104 to the host 100 in the mobile industry processor interface bus 102.
In such a situation, the slave 104 stops transmitting signals to the host 100 and returns to the initial state. However, since the host 100 continues data transmission at the same time, the slave 104 may incorrectly switch to other status from the initial state, which causes abnormal operations (e.g. the host 100 still continues transmitting high-speed differential signals as shown in FIG. 3A, or the host 100 transmits low power signals under other conditions such that the slave 104 operates abnormally).
On the other hand, please refer to FIG. 4, which is a signal diagram of the mobile industry processor interface bus 102 when the host 100 continues transmitting high-speed differential signals at time out of a transmission timer. As shown in FIG. 4, the host 100 starts transmitting high-speed differential signals after transmitting a high-speed transmission sequence. After time out of the transmission timer at a time T, the host 100 should stop transmission and both the host 100 and the slave 104 should return to the initial state according to a specification. However, errors may be occurred in the host 100. The host 100 therefore continues transmitting high-speed differential signals, such that the slave 104 enters the high-speed transmission mode again and derives incorrect data.
As can be seen, the host and the slave in the prior art may consider the status of a single mobile industry processor interface bus shared for data transmission between the host and the slave differently (e.g. statuses of control authority or transmission timer), which causes transmission errors. Thus, there is a need for improvement of the prior art.